The present invention generally relates to integrated circuit fabrication, and more particularly, to a self-aligned three-dimensional chip stack and method for making the same.
A three-dimensional package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. The three-dimensional stack is driven by the strong demand for high speed, high density, small size, and multifunctional electronic devices. When this stack technology is applied in the field of memory devices, it is possible to realize a packaged product having the memory capacity more than two times the memory capacity of an unpackaged chip, for example, and thus it is possible to increase the efficiency of the mounting area usage.